Generally, as shown in FIG. 10, an active matrix display device includes an active matrix panel 101 having pixels aligned in a matrix manner, a signal line driving circuit 102 for driving a data signal line (not shown) in the active matrix panel 101, a scanning line driving circuit 103 for driving a scanning line (not shown) in the active matrix panel 101, a frame memory 104 for storing a digital image signal transferred to the signal line driving circuit 102, and an analog circuit 105 for generating a signal (level voltage) which converts a digital image signal into an analog signal at the signal line driving circuit 102.
The display device further includes a dot clock oscillation circuit (DCK oscillation circuit) 106, an H counter 107, and a V counter 108.
The DCK oscillation circuit 106 oscillates a dot clock for transferring a digital image signal stored in the frame memory 104 to the signal line driving circuit 102 on a frame by frame basis. The dot clock oscillated from the DCK oscillation circuit 106 is supplied to the signal line driving circuit 102 so as to be used as a sampling clock of an image signal.
Further, the dot clock oscillated from the DCK oscillation circuit 106 is also supplied to the H counter 107. The H counter 107 generates a horizontal synchronization series signal based on the dot clock which has been supplied, and this horizontal synchronization series signal is supplied to the signal line driving circuit 102 and the scanning line driving circuit 103.
The horizontal synchronization series signal is used in the signal line driving circuit 102 as an output timing signal of the image signal for determining output timing to the active matrix panel 101, and is used in the scanning line driving circuit 103 as an output timing signal of the scanning signal for determining output timing to an active matrix panel 101.
Further, the horizontal synchronization series signal generated in the H counter 107 is supplied to the V counter 108. The V counter 108 generates a vertical synchronization series signal from the horizontal synchronization series signal, and supplies this signal to the scanning line driving circuit 103 so as to be used as a timing signal for controlling scanning start timing of the scanning line.
FIG. 11 shows respective waveforms of a dot clock (DCK) oscillated in the DCK oscillation circuit 106, a horizontal synchronization series signal (Hsync) generated in the H counter 107 and a vertical synchronization series signal (V sync) generated in the V counter 108 in a display device having the foregoing arrangement.
Note that, since the DCK is higher in speed than the other signals (Hsync, Vsync), the period of this signal is dense (painted black) in the waveform shown in FIG. 11.
In the display device having the foregoing arrangement, the scanning signal line in the active matrix panel 101 is driven at the timings shown in FIG. 14(a). More specifically, the display device carries out display by sequentially applying a ON voltage to the scanning signal lines G(0), G(1), G(2), G(3), . . . so as to turn on TFTs connected to the respective scanning lines. Here, “a scanning period” designates a period where a given scanning line is on. Further, a retrace period is provided between the respective scanning periods.
However, assuming that the active matrix panel 101 is a hold-type display element, which is, for example, a TFT liquid crystal panel, a period for holding a charge by the liquid crystal may be provided between the respective scanning periods. Since the charge is held by the liquid crystal in this period, no voltage application is necessary to the liquid crystal. Therefore, the driving circuits for driving the active matrix panel 101 are not required to be driven in this period. This period is referred to as an inaction period.
A display device as an assumable example to realize such a driving method is shown in FIG. 12. This display device including an inaction control circuit 109 for stopping driving circuits, i.e., a signal line driving circuit 102, a scanning line driving circuit 103, and an analog circuit 105.
The inaction control circuit 109 generates a scan signal (Scan signal) shown in FIG. 13 from a horizontal synchronization series signal generated in the V counter 108, and supplies the Scan signal to the signal line driving circuit 102, the scanning line driving circuit 103, and the analog circuit 105.
The Scan signal is a binary signal whose level becomes high in the scanning period and becomes low in the inaction period. Accordingly, if the device is arranged to carry out operations of the signal line driving circuit 102, the scanning line driving circuit 103 and the analog circuit 105 when the level of the supplied Scan signal is high, and to stop their operations when the level is low, power consumption in the inaction period can be reduced. Such a technology is disclosed in Japanese Unexamined Patent Publication No. 312253/2001 (published on Nov. 9, 2001 (Corresponding U.S. Pub. No. 2002/0180673A1)).
Here, with reference to FIGS. 15(a) and 15(b), the following will explain the respective power consumptions in case of performing the driving method for a display device shown in FIG. 14(a) and the driving method for a display device shown in FIG. 14(b).
FIG. 15(a) shows power consumption of the driving method for a display device shown in FIG. 14(a), and FIG. 15(b) shows power consumption of the driving method for a display device shown in FIG. 14(b).
In the driving method for a display device shown in FIG. 14(a), the all circuits included in the display device are always in operation, and therefore, as shown in FIG. 15(a), power consumption in one frame period is equal to the average power consumption of the display device. In this case, it is assumed that power consumption in one frame period is 10 mW.
On the other hand, in the driving method for a display device shown in FIG. 14(b), among the circuits included in the display device, the signal line driving circuit 102, the scanning line driving circuit 103 and the analog circuit 105 are controlled to stop their operations in a non-refresh period (the inaction period), and therefore the power consumption is high in a refresh period (the scanning period) and low in the non-refresh period, thus reducing average power consumption of the display device.
Incidentally, since the display device shown in FIG. 12 is arranged so that a signal (horizontal synchronization series signal, vertical synchronization series signal) for determining a frame for scanning and a frame for non-scanning is generated based on a dot clock from the DCK oscillation circuit 106, the DCK oscillation circuit 106 is driven even in the non-refresh period.
Besides, the DCK oscillation circuit 106 consumes great power due to the function for generating a high-speed clock such as a timing clock used in the refresh period for determining such as writing timing.
Therefore, even though reduction of the average power consumption is attempted by using the driving method for a display device shown in FIG. 14(b) which can reduce power consumption in the inaction period, the operation of the DCK oscillation circuit 106 which consumes more power than the other driving circuits (the signal line driving circuit 102, the scanning line driving circuit 103 and the analog circuit 105) in the non-refresh period prevents the power consumption in the non-refresh period from being greatly reduced.
For example, when the DCK oscillation circuit 106 operates at 500 kHz, the power consumption is found as 2 mW according to the graph shown in FIG. 16. That is, the average power consumption in the non-refresh period shown in FIG. 15(b) becomes close to 2 mW.
Here, assuming that the power consumption in the refresh period is 10 mW, and the power consumption ratio of the refresh period to the non-refresh period is 1:9, the average power consumption is found as follows.(10 mW×1+2 mW×9)/10=2.8 mW.
If the ratio of non refresh period is increased, the average power consumption can be decreased; however, the average power consumption still only becomes closer to 2 mW, i.e., the power consumption in the non-scanning period, and the reduction cannot go further. More specifically, it is impossible to reduce the power consumption less than the power consumed in the circuits operating in the non-refresh period.